EDA Glossary

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z Other Glossaries
A
 

analog
An electronic signal which consists of a variable wave that moves up and down continuously, as is found in the physics of all natural processes such as sound and light. Analog electronic devices are less common than digital ones because the mathematical description of an analog circuit is highly complex, as opposed to a digital signal which consists of just two discrete states — either on or off.

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analog simulator
An EDA software tool which simulates the behavior of analog signals.

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  analysis tools
EDA software tools or tool suites which may display simulator output for analysis (as in waveform analyzers) or which may analyze the reliability, electromagnetic interference, metal migration, signal integrity, or thermal characteristics of a design. The tools in this category may work at any level of abstraction — behavioral, register-transfer-level (RTL), gate-level, or with the physical layout of an IC device or electronic system.

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  API (Application Programming Interface)
A procedural interface between two applications or between an application and user-supplied data.

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  application
A computer program which is intended to perform a specific task. An application includes an executable file which is invoked to run the desired program. See also tool.

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  ASIC (Application-Specific Integrated Circuit)
The common name for semi-custom integrated cicuits. A type of chip which is composed of standard building blocks called cells that are designed to implement a specific customer application. These may include digital, linear, and mixed-level circuits. See also full-custom IC.

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  ASP (Application Service Provider)
A business model whereby applications (which may include EDA hardware as well as software-based tools) are hosted by an Internet-based supplier and made accessible to end users across the Web on a pay-per-use basis. In a different context, ASP may stand for Average Selling Price.
  ATE (Automated Test Equipment)
Manufacturing equipment used to perform electrical testing of integrated circuits.

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  ATPG (Automatic Test Pattern Generation)
The process of automatically generating the test vectors required to produce a high-fault-coverage test pattern for a design.

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B
  back-annotation
The process of extracting specific types of data from a design representation and transporting it back to other representations of the design or library for iterative use in earlier steps of the design flow. For example, the path delays from a nearly finished design layout are often back-annotated for use by simulation tools to achieve accurate post-layout verification.
  behavioral modelingSystem-level modeling consisting of a functional specification plus modeling of the timing of an implementation. A behavioral model consist of an HDL description of a device or component which is expressed at a relatively high level of abstraction (higher than the register-transfer level or gate level). It uses underlying mathematical equations to represent the functional behavior of the component. See also functional modeling.

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  benchmark
A design test case which is used to measure the capabilities, limitations, and breakthroughs reported for newly proposed and existing algorithms and tools.

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  BIST (Built-In Self Test)
The capability of a product to perform a functional test of itself. Some support from external equipment may be required. BIST usually involves special logic circuitry in the product to generate input stimuli and analyze test responses.

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  block
A group of interconnected cells. A block may contain instances of other blocks.

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  bottom-up design
A design methodology whereby the designer starts with the most basic or primitive components and incrementally builds up the system into higher-level components.

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  breadboard
A printed circuit board on which experimental electronic circuits can be developed; so-called from the time when radios were constructed at home on a breadboard.

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C
  CAD (Computer-Aided Design)
The electronic design automation of projects that were previously under manual methods considered to be drafting functions; typically refers to PCB layout, wire harness design, or mechanical design.

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  CAE (Computer-Aided Engineering)
The electronic design automation of projects that were previously under manual methods considered to be electronic engineering functions, such as the design of integrated circuits and computing devices.

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  CAM (Computer-Aided Manufacturing)
Electronic design automation applied to the manufacturing process. Involves the planning, scheduling, simulation, and control of advanced manufacturing systems.

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  cell
An individual component of a technology library. Typically a logic gate (for example, a 2-input NAND gate). See also primitive and gate.

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  cell library
A repository of all of the components in a collection of gate-array macrocells.

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  chip
Semiconductor components which provide the memory, logic, and virtually all other intelligence functions in an electronic system. Also known as a microchip, chip, integrated circuit or IC. See also IC.

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  CIS (Component Information System)
An EDA or supply chain application which allows users to locate components and suppliers, view parametric information about the component, conduct procurement transactions, and in some cases to even obtain design views of the selected components that can drive their particular EDA design tools of choice. Also referred to as CSM (Component Supplier Management).

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  CMOS (Complementary Metal Oxide Semiconductor)
The dominant semiconductor technology for microprocessors, memories, and application specific integrated circuits (ASICs). In CMOS technology, both N-type and P-type transistors are used to realize logic functions. The main advantage of CMOS over NMOS and bipolar technology is the much smaller power dissipation. A CMOS circuit has almost no static power dissipation, since power is only dissipated when the circuit actually switches. This allows many more CMOS gates to be integrated on an IC than in NMOS or bipolar technology, resulting in much better performance.

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  construct
A syntactical unit in a textual design language such as C/C++, Verilog, or VHDL. A construct may be a declaration, a statement, or an expression.

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  convergence
Achievement of a final design solution in which all design constraints have been successfully met. Often this involves balancing and trading off two or more requirements that are in opposition with one another, such as timing delay versus area.

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  core
A reusable block of semiconductor intellectual property. See also SIP.

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  CSM (Component Supplier Management)
See CIS (Component Information System).

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D
  design cycle
The period of time required to complete an electronic design of any type, from concept to production.

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  design entry
The process of creating a new design of any type — chip, board, module, or system — using textual and/or graphical tools such as schematic capture or other high-level graphical methods, hardware description languages, Boolean equations, or other methods. Also referred to as design capture.

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  design flow
A series of connected processes for performing a complete design cycle.

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  design flow
The sequence of steps required to complete a chip design process from concept to production.

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  design for reuse
The methodology associated with the practice of reusing previously designed building blocks of logic in a chip, PCB, or system design. See also SoC (System on Chip).

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  DFM
Design-for-Manufacturing

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  design management
EDA software tools which automatically manage design data and the design process by controlling the operation of one or more EDA tools.

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  design reuse
The practice of taking part of an existing design and using it in another design with minimal rework. See also design for reuse and SIP.

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  design services
Consulting services offered to an individual customer to assist in designing chips, printed circuit boards, multi-chip modules, or systems, as well as design environments and libraries. May also consist of product installation, training, and field application support, and.as well as the delivery of Semiconductor Intellectual Property (SIP) products, designs, libraries, retargeting, etc.

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  design specification
A summary of the features and performance targets that are intended for a new electronic product.  This specification drives the requirements and/or constraints that must be met during the design and manufacturing processes.

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  DFT (Design For Testability)
The practice of defining an ASIC manufacturing test strategy at the start of the design process rather than at the end.

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  die
A bare integrated circuit etched onto a multilayer substrate such as silicon or gallium arsenide which has passed through the IC manufacturing process but which has not been attached to leads and packaged within a chip carrier. Plural: dice

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  digital
Electronic signals or switches based on discrete binary electrical levels (ones and zeros) found in such products as touch-tone telephones and audio compact disk players. These signals are either on or off, high or low, yes or no.

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  disaggregation
The macroeconomic trend toward using a variety of different suppliers, where specific portions of the design-to-manufacturing flow are outsourced to specialized service vendors which may be located in widely dispersed geographical regions. This trend represents movement away from the more traditional model of vertical integration (or “one-stop shopping”), whereby a system house procures most of its design and fabrication services from a single source.

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  DRC (Design Rule Checkers)
Software tools which verify that the layout topology of circuits which have undergone placement, routing, and compaction does not violate any rules associated with the target process technology. Includes electrical rule checkers (ERC), which verify that no electrical rule violations have occurred, and layout-versus-schematic checkers (LVS), which verify that the physical implementation of the design matches the logical implementation.

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  DSM (Deep SubMicron)
A semiconductor process technology having a feature size of 0.5 microns or less.

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  DSP (Digital Signal Processor)
A specialized semiconductor device which is specialized for performing conversions between analog and digital signals. DSPs are widely used in products involved with audio and video, such as sound cards, fax machines, modems, cellular phones, hard disks, and digital TVs. DSP chips are used on sound cards for recording and playback as well as speech synthesis.

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E
  ECO (Engineering Change Order)
A specification of the minor and valid engineering changes that are desired to be made to a netlist before a chip is manufactured.  Requires the “clustering” of the new netlist to look like the original one, placement of all components as in the old floorplan, and resolution of the hierarchical location and floorplan placement of new instances that were not part of the original netlist.

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  EDA (Electronic Design Automation)
The industry which is involved in developing and supplying highly specialized software- and hardware-based tools for the automated design of electronic products of all kinds.  EDA products and services are essential for the design of electronic products that enable many other high-tech sectors of the economy, such as computers, communications, consumer, industrial, military/aerospace, semiconductors, and transportation.

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  EDIF (Electronic Design Interchange Format)
A textual language designed to enable the transfer of all forms of electronic design information between different CAD systems. Currently implemented for netlist and schematic descriptions, although there are still significant differences between different tool vendor implementations which may impair portability.

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  embedded system
An application-specific computing system that is designed into a product so invisibly it is not apparent to end users that they are using a computer. Examples are found in automotive anti-lock braking systems, microwave ovens, and automatic dishwashers. The computing processor inside an embedded system typically makes use of a real-time operating system which does not require a waiting period to boot up.

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  EMC (Electromagnetic Compatibility)
Describes how an electronic device will behave in a "real world" setting of EMI, as defined by the environment and the intended application. Different EMC/EMI standards and specifications are imposed based on the classification of an electronic device and its environmental application.

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  EMI (Electromagnetic Interference)
The electronic noise in an environment that can affect an electronic device, or is being produced by an electronic device, or both. EMI analysis tools are used to verify EMC compliance during the design of high-speed PCBs and IC packages. The traditional EMI remedies involve the addition of extra components, metal shields, metal plans, or even redesigning the entire system. Synonym: radio-frequency interference.

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  emulation
The process by which a device under development and its native software is prototyped before its manufacture.

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  emulators
A class of EDA products which includes both specialized computing hardware and software. Emulators are used to prototype a design and exercise its native software prior to its manufacture. Many emulators can also be used to perform hardware acceleration of simulation runs.

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  encapsulation
1) The preparation of a tool for integration into design frameworks without any changes to the source code for the tool. 2) The preparation of a block of SIP for integration into systems without any changes to the source code for the SIP.

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  equivalency checking
A formal verification technique which verifies the integrity of each design step by proving the functional equivalence between two implementations.

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  ERC (Electrical Rule Checker)
EDA software tools for checking the electrical integrity of complex digital, memory and mixed-signal circuitry.

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  event-driven simulator
An EDA software tool that simulates the behavior of a logic design which has been described at some level of abstraction (behavioral, RTL, or gate-level), considers timing information in the simulation process, and thus must schedule events and evaluate signals between clock cycles.

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F
  fab
A shorthand term for “fabrication facility.” In this context, refers to a semiconductor manufacturing facility.

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  fault grade
A measurement of the efficiency of test vectors to detect manufacturing defects in bare-die chips. The fault-grade value is usually presented as a percentage of the stuck-at faults that can be identified using those test vectors.

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  floating license
A license which is not bound to a specific workstation; that is, which may “float” among multiple workstations that are connected via a network. See also node-locked license.

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  floorplan
The high-level physical layout of blocks on a semiconductor device (either chips or boards). Floorplanning tools also typically provide estimations of timing delays.

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  floorplanners
EDA software tools that provide an environment where issues such as timing, area, power dissipation, and routeability can be analyzed before a detailed physical layout of a design is completed. These tools provide interactive and/or automatic capability to accurately estimate interconnect resistance/capacitance (RC) and predict timing delays before the placement and routing of the design so that users can evaluate and choose the optimum floorplan.  Includes software tools for creating high-level graphical depictions of the topology on an integrated circuit layout. This process is also referred to as design planning.

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  formal verification
Use of various types of formal methods (abstract calculus) to verify the correctness of IC logic or system interactions. Equivalency checking is the most common formal verification method, which is used to compare the design that is being created against a design that is already proven accurate. Model checking is another method that ascertains the behavior of a specific signal at a certain time. Semi-formal is a newer method which combines formal verification and simulation.

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  forward annotation
The addition of data to a design to influence future steps in the design flow.  In the submicron gate-array design flow, it is possible to forward-annotate timing constraints for use during the IC layout process. See also back-annotation.

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  foundry
A “for-hire” manufacturing facility for integrated circuits. A foundry manufactures chips for external (“fabless”) customers. A captive foundry, on the other hand, manufactures chips for only a single company and is generally referred to as its “fab.” The term foundry may also refer to a PCB manufacturing facility.

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  framework
A computing architecture for integrating products from multiple vendors which includes data representation, design data management, methodology management, a user interface, an extension language, and inter-tool communication.

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  FSM (Finite State Machine)
A model of computation consisting of a set of states, a start state, an input alphabet, and a transition function which maps input symbols and current states to a next state.  Computation begins in the start state with an input string, and it changes to new states depending on the transition function. There are many variants of an FSM;  for example, machines having actions (outputs) associated transitions (Mealy machines) or states (Moore machines), and others.

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  full-custom IC
A IC whose lowest-level circuit layout has been custom crafted using polygon editors, symbolic editors, and compactors.

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  functional modeling
System modeling that specifies input/output behavior without specifying its timing. See also behavioral modeling.

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  functional verification tool
An EDA software application that verifies the functional correctness of a hardware design by employing logic simulation techniques.

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G
  gate
Another name for a logic cell, which is a functional group of transistors having physical attributes that support a specific semiconductor process technology.

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   gate count
A metric for the size of an ASIC design, usually expressed in terms of the equivalent number of basic 2-input NAND gates used. A gate count can be roughly converted to a transistor count by multiplying by a factor of four.

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  gate count
A metric for the size of an ASIC design, usually expressed in terms of the equivalent number of basic 2-input NAND gates used. A gate count can be roughly converted to a transistor count by multiplying by a factor of four.

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  GDSII
A term often used in a generic sense to refer to graphical IC or PCB layout data in an interchange format.  In the generic sense, the term GDSII is frequently used even if the source data format is GDSIV or other graphical format. In the strict sense, GDSII is a specific data format developed and trademarked by Calma/GE and implies use of a Calma graphics system. The term stream format is the standard output format for GDSII or later format data on the Calma systems used in data interchange, and it more accurately describes the data format actually used in interchanges. Stream format is a hexadecimal description in variable-length records which is used to describe graphical data.

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H
  handoff
The process of transferring a finished design database to an ASIC vendor or foundry for layout and prototype fabrication. Also referred to as signoff.

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  hard macro
A block of semiconductor intellectual property (SIP) containing a logic function expressed as a process-specific layout that is fixed and proprietary. Usually its internals are protected from view and modification by the user, rather than being resynthesizable. See also macrocell and soft macro.

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  hardware modeling
The process of defining the functionality of a component using an actual chip rather than a software description. Often employed in the early life of a chip when physical prototypes are available, but a software model is not.

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  hardware/software co-design
Software tools that perform or support hardware/software partitioning, performance evaluation, and design entry for system-level designs that are comprised of both hardware and software elements, as in embedded systems. Includes tools and interfaces that link the design and evaluation steps with code compilation models.

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  HDL (Hardware Description Language)
One of several specialized high-level languages used by semiconductor designers to describe the features and functionality of chips and systems prior to handoff to the IC layout process. HDL descriptions are used in both the design implementation and verification flows. Currently, the two standard HDLs in use worldwide are Verilog HDL and VHDL. Several proprietary HDLs also exist, mainly for describing logic that is targeted for vendor-specific programmable logic devices.

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  heterogeneous network
A network consisting of more than one type of hardware platform.

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  hierarchical design
A design methodology where portions of large designs are divided into manageable sections or sub-blocks that may be created, represented symbolically, designed, and then connected together when completed. This methodology allows different parts of the design to be worked on in parallel.

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I
  IC (Integrated Circuit)
A semiconductor device containing large numbers of electronic circuits. ICs are the major building blocks of electronic systems such as cellular phones, pagers, and personal computers. Also referred to as a semiconductor device or chip.

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  implementation
The result of the design synthesis process, in which an abstract description of a design entity is converted into gates and the electrical connections between them (signals).  An implementation is rendered using components from the foundry-specific design library that represents the target semiconductor process technology. Many of the physical analysis algorithms that were previously found only in standalone physical analysis tools are now being integrated into the implementation flow to help drive the synthesis process.

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  instance
A copy of a library cell or block which has been called into a design and made specific by naming it and connecting it to other logic in the design. This process is known as instantiation.

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  I/O (Input/Output)
An input, output, or bidirectional buffer cell used to connect design interface signals directly to package pins.

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  IP (Intellectual Property)
A broad category of written and electronic material that is legally recognized as proprietary to a specific organization.  In the electronics field, intellectual property refers to specific portions of a chip or “building blocks” which may be proprietary and/or patented designs of a particular company. These reusable blocks or “cores” may be made available commercially to others as portions of new designs. See also SIP (Semiconductor Intellectual Property) and VC (Virtual Component).  In a different context, IP stands for Internet Protocol.

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J
  JTAG (Joint Test Action Group)
1) The committee that established the test access port (TAP) and boundary-scan architecture defined in IEEE Standard 1149.1-1990.  2) The common name for IEEE Standard 1149.1-1990.

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L
  layout
For ICs, the process of floorplanning, implementing, and verifying the location of transistors and their connections within a chip design.  For PCBs, the process of entering, placing, routing, and verifying the location of physicial components and their connections within a board design.

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  layout verification
The process of verifying that the layout topology of circuits which have undergone placement, routing, and compaction does not violate any fabrication process rules.  Includes Design Rule Checkers (DRS), Electrical Rule Checkers (ERC), and Layout-Versus-Schematic Checkers (LVS).

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  library
A collection of design objects that are related in some way, such as simulation models, symbols, or footprints. The objects may be part of a single design, in which case it would be a design library. The objects could be standard-cell elements for IC design, or components for PCB design, in which case it would be a reference library.

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  license
A unit of measure for a software usage authorization. A license may be node-locked or floating. Also known as a key.

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  logic
The sequence of functions performed by hardware or software. Hardware logic is made up of circuits that perform an operation. Software logic is the sequence of instructions in a program.

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  LSI (Large-Scale Integration)
Refers to the placement of thousands of electronic components on a single integrated circuit.

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  LVS (Layout Versus Schematic)
An EDA software tool which compares a finished layout with the schematic and ensures that the physical implementation of a circuit matches its logical definition.

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M
  macrocell
A large core or SIP block. Sometimes referred to as star IP.

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  MCM (Multi-Chip Module)
A type of board technology whereby multiple, unpackaged integrated circuits (bare die) are mounted — along with signal conditioning or support circuitry such as capacitors and resistors — on a single laminate or ceramic base material. The MCM footprint is much smaller than conventional single chip packages, resulting in a smaller motherboard and smaller space requirements for panels, enclosures, and cabling. The result is a high-density module that resembles a single component when mounted on a printed circuit board. By combining more circuit functions in an MCM, fewer system assemblies are required, resulting in lower circuit design costs, integrated functional testing, and higher manufacturing yields.

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  mixed-signal simulators
Software tools that simulate the behavior of mixed analog and digital portions of a design.  Includes interface packages for linking analog and digital signals.

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  model
A functional representation of a device or system that is delivered in object code format.  This software representation contains the basic structure and characteristics of a design object which is used to perform design verification. During the development of an electronic system, models are exercised along with signals entering from the outside environment (vectors) to simulate the behavior of the system in software and ensure that it will operate properly before being manufactured in hardware.

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  model checking
A formal verification technique which compares the functionality of a design to a set of user-specified properties or characteristics. Determines whether a set of conditions or properties hold true or are contained within a given implementation of a design. Also referred to as property checking.

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  module generators
Tools used exclusively to generate SIP from regular parameterizable physical structures that are based on a fixed set of base leaf cells. Includes tools to create integration views for SIP blocks created by the Module Generator. Module generators (which are also termed target compilers) produce physical blocks from a set of design parameters that are based on physical and electrical design rules.

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  MSI (Medium-Scale Integration)
An integrated circuit (IC) having 100 to 10,000 elements.

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N
  net delay
The largest single component-to-component delay on a net. For example, if the component-to-component delays between two sets of components on the same net are 2 nanoseconds and 4 nanoseconds, the net delay will be the larger of the two, or 4 nanoseconds.

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  netlist
A textual file representing an ASIC design as a set of library-specific cells along with their interconnections.

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  NFS (Network File System)
A protocol developed by Sun Microsystems which allows a computer to access files over a network as if they were on its local disks.

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  node-locked license
A license which is bound to a specific workstation. See also floating license.

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O
  OMF (Open Model Forum)
A standards committee that promulgates a standard interface between simulators and reusable models.

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  OMI (Open Model Interface)
The standard interface developed by the OMF committee.

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  optimization
Use of a computing algorithm to achieve the most efficient design of a product. Various types of optimization are performed by different tools in the design flows for chips, boards, and systems.

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P
  parameter
A means by which an application or user can customize the behavior or characteristics of a model instance when it is created. A parameter is set to a constant value during design entry.

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  parasitic extraction tools
Software tools that translate IC layout data into networks of electrical circuit elements (transistors, resistors and capacitors) and parasitic elements (interconnect capacitance and resistance). These tools are used to model the timing, power, and signal behavior of an IC design. Also included in this category are network reduction tools and delay calculators.

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  pattern
An arrangement of services that collectively model a communication path from sender to receiver. Patterns support the modeling of communication between software and hardware, hardware and software, software and software, or hardware and hardware.

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  PCA (Printed Circuit Assembly)
The manufacturing assembly of printed circuit boards, multichip modules, and hybrids of these two. Includes printing, pasting, component placement, reflow, wave soldering, cabling, and test.

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  PCB (Printed Circuit Board)
An electronic interconnect product which is the foundation of most electronic systems.  PCBs are used to mount and interconnect chips, capacitors, resistors, and other discrete components required in a piece of electronic equipment. The base material of a PCB is called a dielectric and is generally made of rigid fiberglass, rigid paper, or flexible thin plastic laminates. Those dielectric substrates are then coated with copper and may be fabricated into rigit single- or double-sided, multilayer, or flexible circuits. Also referred to as printed wiring board.

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  PCB libraries and library tools
Descriptions of design elements used for designing PCBs or larger systems. Includes component models for simulation or analysis, symbols, component information systems, library development tools, library management tools, and design libraries for PCB or system-level design.

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  PCB/MCM layout tools
Physical design tools for the placement of physical components and/or the routing of interconnect signal traces on printed circuit boards (PCBs) and multi-chip modules (MCMs). A a PCB/MCM layout tool has the capability to determine the placement of components and to route their interconnect wiring. A PCB/MCM layout tool may also include capabilities for design rule checking, photoplotter output creation, and interfaces to manufacturing.

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  PCI (Peripheral Component Interconnect)
An industry standard for the bus structure connecting the peripheral components of a personal computer, such as the monitor, keyboard, mouse, etc.

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  PDM (Product Data Management)
Data management systems which manage both attribute and documentary product data, as well as relationships between them, through a relational database system.

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  performance model
A model that estimates one or more physical or temporal characteristics such as signal delay, power usage, area, temperature, electromagnetic interference, etc.

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  physical macrocells and libraries
Logic and circuit functions delivered in a form that represents their physical layout and footprints. The physical layout representations are in GDSII or CIF format and are targeted to a particular set of fabrications process design rules. Physical libraries may include views such as simulation models, graphical symbols for schematics, and routing abstractions.

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  placement & routing
The process of placing and routing the circuitry of an integrated circuit (IC) or application-specific integrated circuit (ASIC) using tools for designing gate arrays, embedded arrays, standard cells, and irregularly sized macrocell or mega-cell blocks.

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  placement rules
User-defined rules which force a special placement group. May be defined for a given technology library or a specific netlist.

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  PLD (Programmable Logic Device)
1) A high-level term for all types of programmable semiconductor chips, including the FPGA (Field-Programmable Gate Array), CPLD (Complex Programmable Logic Device), EPLD (Erasable Programmable Logic Device), simple PLD, and others such as the EPROM and EEPROM.  2) A simple PLD (archaic).

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  PLDE (Pre-Layout Delay Estimation)
Estimate of interconnect timing and capacitances used to increase accuracy in timing verification of designs before committing to layout.

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  ports
Objects in design description that allow the model and the application to interact during simulation. Ports may be of the types Input, Output, or I/O (bidirectional).

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  power analysis tools
EDA software tools that analyze, optimize, or diagnose power problems, or provide automatic power reduction in electronic circuits.

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  pragma
A structured comment which is added to precompiled code.

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  primitive
An instance of a cell at the lowest logic level on a circuit. Multiple instances of the same cell may exist in a design.

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  process technology
The conditions required for a given semiconductor manufacturing process, characterized within the cells of a technology-specific library.

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  process window
A rectangular or elliptical area in an Exposure-Focus contour plot within which a semiconductor fab controls its process.

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  production test
The process of verifying that a device has been manufactured correctly before it leaves the manufacturing facility.

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  product lifecycle tools
Supply chain tools which are used to track the entire lifecycle of a finished product once it leaves the manufacturing facility. Includes installation, training, field support, and sales tracking.

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  property checking
A formal verification technique which verifies that a design does or does not conform to a specified property under all possible sets of legal input conditions. See model checking.

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  proprietary SIP
Commercially available Semiconductor Intellectual Property (SIP) blocks based on unique architectures invented by an SIP developer. Includes micro-processors, digital signal processors, special-purpose processors, microcontrollers, memory architectures, etc.

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Q 
  qualified parts list
A list of those suppliers and/or devices that have been qualified for a given program, specification, or set of specifications.

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   quality conformance inspection
Sample tests performed on a periodic basis that determine conformance of quality and reliability standards and ensure a continuing level of quality for the device type under test.

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 R
  random logic
Components and signals which exist at a low level of hierarchy, outside of the major blocks of logic in a design. Sometimes referred to as glue logic because its function may be to connect the major hierarchical blocks. See also primitive.

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  retargeting
The process of converting a design from one semiconductor process technology to a different one. Requires the resynthesis of the design using a different technology library.

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  RC
Resistance and capacitance, two physical issues that are always traded off in the design of an electrical circuit.

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  RF (Radio Frequency)
Any frequency within the electromagnetic spectrum normally associated with radio wave propagation (lower than 3000 GHz).

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  routability
The level of effort required to automatically route the connections (or nets) in a design based on the available routing resources, such as space between components, grid width, numbers of layers, etc.

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  RTL (Register-Transfer Level)
A type of HDL description in which a circuit is modeled by specifying the data flowing between a set of registers, which are elements of a design that transition between states based on an event (a high or low edge) occurring on a clock signal. The register-transfer level of abstraction is above the gate level and below the behavioral level.

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  RTOS (Real-Time Operating System)
One of various computer operating systems that are typically used in embedded systems which do not require a waiting period to start up.

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S
  schematic capture
A graphical design entry process used to create gate-level schematics which represent logic in a design.

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  semiconductor
See IC (Integrated Circuit).

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  signal integrity analysis tools
EDA software tools that analyze electrical signal behavior of wiring networks on printed circuit boards (PCBs), integrated circuits (ICs), IC packages and sockets, multi-chip modules (MCMs), and other structures such as hybrids. May include two-dimensional or three-dimensional field solvers.

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  silicon
The most commonly used element in semiconductors due to its ease of processing and abundance (silicon is the element found in sand). Chips are made by growing silicon into a giant crystal, which is sliced into thin, round wafers, polished and coated with chemicals, and layers of patterns are etched into the wafer. The wafer is then cut into small squares and packaged in ceramic or laminate carriers, connecting the parts of the chip to the outside system using tiny gold wires or other techniques such as ball-grid arrays. The chip is ultimately placed into a final electronic product, such as a cell phone or a computer.  Silicon is not the only substrate on which chips are manufactured, however, some of the others being gallium arsenide and silicon germanium.

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  siliconization
The trend toward designing more and more logic in a system onto the chip.

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  simulation
The process of verifying an electronic design using EDA software which reads in models and input/output vectors, exercises the device under test, and records the resulting behavior and timing for the purpose of identifying and debugging any incorrect or unexpected behavior.

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  SIP (Semiconductor Intellectual Property)
A block of a design or testbench that can be reused. Also known as a virtual component.

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  SoC (System on Chip)
A single chip on which multiple specialized blocks of logic have been combined. These blocks, which consist of Semiconductor Intellectual Property (SIP), may be sourced from a company’s internal portfolio, or from commercial providers who are external to the company.

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  soft macro
A gate-level netlist description of a logic function supplied by an SIP vendor as a standard library part (for example, a counter). See also macrocell and hard macro.

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  SPICE (Simulation Program with Integrated Circuit Emphasis)
An industry-standard analog simulation language which contains models for most circuit elements and can handle complex nonlinear circuits. Also refers to a freely distributed simulation tool which simulates circuitry described in the SPICE language.

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  SSI (Small-Scale Integration)
An integrated circuit (IC) having fewer than 100 elements.

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  standalone
A mode in which a computer can run only locally installed and licensed applications.

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  standards-based SIP
Commercially available SIP blocks that implement either a de facto (unofficial but commonly used) or a de jure (officially ratified) industry standard. Includes bus interfaces, encoders/decoders for audio and video standard formats, communications interfaces, etc. Examples are PCI, JPEG, MPEG, USB, and FireWire (IEEE 1394).

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  static timing analysis
The process of detecting timing violations in a digital design by checking the clock frequency using software tools with appropriate gate-level and interconnect delay models.

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  STD (State Transition Diagram)
A graphical representation of a finite state machine (FSM). Also referred to as a state diagram.

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  symbol
A graphical representation of a component that contains information about the ports of the component. Each symbol has a corresponding textual interface file that contains the same information as the graphical representation. Both the symbol and interface files are views of the component.

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  synthesis
An EDA process which reads a high-level electronic design description and implements it at a lower level of abstraction. Synthesis tools typically include algorithms for logic optimization and technology retargeting. Legacy synthesis tools produce a gate-level implementation, at which point the design netlist is handed off to the IC layout process.  More recent developments have synthesis becoming more tightly integrated with the IC layout process in order to better achieve convergence of goals such as timing.

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  synthesizable macrocells and cores
Functional blocks of logic which are described in a hardware description language and can be implemented by the user through synthesis as a corresponding gate-level netlist using the process technology of choice. See also macrocells and cores.

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T
  target compilers
See module generators.

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  technology flow
A specific manufacturing line from design, fabrication, assembly, packaging, through to test in a given technology.

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  test automation tools
EDA software tools that enable and facilitate the testing of electronic designs during the manufacturing process and beyond. Includes automatic test vector generation (ATPG) and test insertion, including built-in self test (BIST) logic.

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  test insertion
The automatic insertion of test logic, including scan cells and test access ports, into the circuitry of a chip or PCB design to enable quality testing during the manufacturing process.

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  testbench
A custom model of the system environment used during the verification of a design to provide simulation inputs and respond to simulated outputs from the design under test.

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  timing-driven design
A methodology to achieve circuit performance goals, encompassing tools across the entire design flow.

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  tool
In the electronic design automation industry, a shorthand term for an EDA product.  Generally consists of a software application, but in some cases may include specialized hardware, as in emulation, hardware acceleration, and rapid prototyping systems.

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  top-down design
A design methodology whereby an entire design is decomposed into its major components, and then these components are further decomposed into their major components, etc. The advantage is that validation of the behavior takes place before the actual implementation occurs. The constraints are established early in the design flow, and then are passed on and adhered to by the back-end processes.

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  transistor
An electrical switch which is the most basic logic element in an integrated circuit.  Transistors are used to amplify a signal, or to open and close a circuit. Today, tens of millions of transistors can often be found on a single chip.

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  transistor-level simulation tools
High-capacity circuit simulation tools which accept a SPICE netlist as input. These tools are capable of processing millions of transistors.

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U
  use case
A specific way in which some set of users wants to employ a service, tool, or a machine.

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  user
A person who uses application software and who is not the system administrator. In EDA, this person is generally an electronic engineer or a layout designer.

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  user-specific array
A custom base array designed for a specific design application or set of applications. Can support full-custom cells, including memories.

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V
   
VC (Virtual Component)
A reusable block of semiconductor intellectual property (SIP). VCs may be soft (synthesizable), firm (parameterizable), or hard (where the layout is fixed, with only the I/Os visible to the design tools).

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  vectors
A set of values which are used as input to a functional simulator to represent the expected or possible signals coming into a device or system under test.

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  verification
The process of verifying the functional and performance requirements of a design, be it a chip, board, or system. Many different kinds of verification tools are in use today, including simulation, formal verification, various types of physical analysis tools, emulation, and rapid prototyping. Most design verification strategies employ many or all of these approaches to assure the reliability of the final product prior to its manufacture.

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  Verilog HDL
One of two standardized hardware description languages used to specify the structure and behavior of electronic systems in textual format. Developed in the mid-1980s as a proprietary language and acquired by Cadence Design Systems, it became a de facto industry standard. In the mid-90s Cadence placed it into the public domain and it became a de jure standard promulgated by the Institute of Electric and Electronic Engineers (IEEE).  Verilog is also the name of a legacy simulation tool offered by Cadence.

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  VHDL (VHSIC (Very-High-Speed Integrated Circuit) Hardware Description Language)
One of two standardized hardware description languages used to specify the structure and behavior of electronic systems in textual format. Supports behavioral, register-transfer-level (RTL), and gate-level logic descriptions. Developed by the industry in the mid-1980s through funding by the U.S. Department of Defense, VHDL is a de jure standard promulgated by the Institute of Electric and Electronic Engineers (IEEE).

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  view
One of possibly several representations of a component containing information required to drive a particular tool in the design flow.

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  VLSI (Very Large-Scale Integration)
The process of placing thousands (or hundreds of thousands) of electronic components on a single chip.  Nearly all modern chips employ VLSI architectures, or ULSI (ultra-large-scale integration). The line between VLSI and ULSI is vague.

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W
  wafer fab
A clean-room facility where wafers of silicon, gallium arsenide, or other semiconductor substrates are manufactured. Wafers then become the raw material for the IC fabrication process.

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  WAN-based license
A license which may legitimately float among multiple users across a company’s internal Wide-Area Network (WAN), which may connect geographically dispersed sites around the world.

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  workstation
A desktop computer which has sufficient capabilities to run as a standalone system, but which is typically connected to a network to gain access to other computing resources, peripherals, and communications.

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Other Glossaries

For further information on additional terms, the following are available:

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Acknowledgements

EDA Glossary was researched and written by Rita Glover of EDA Today, L.C. under contract to the EDA Consortium. While we make efforts to assure accuracy, we understand that the industry changes constantly and we may have errors or omissions. If you find what you believe to be an error or omission, please contact us with correction or additional information. We will be pleased to review your contribution for inclusion in our glossary.

The following companies and universities graciously permitted the use of their internally generated glossaries and other definition sources:

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Notice a Need for Corrections?

Any corrections and additions to this Glossary are welcomed. This is intended to be a living document and will be updated regularly. Please contact us with your sugested changes.

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